• DocumentCode
    1962258
  • Title

    FPGA implementation of median filter

  • Author

    Maheshwari, Rajul ; Rao, S.S.S.P. ; Poonacha, P.G.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
  • fYear
    1997
  • fDate
    4-7 Jan 1997
  • Firstpage
    523
  • Lastpage
    524
  • Abstract
    This paper gives the algorithm and implementation details of a sliding real time 3×3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques
  • Keywords
    field programmable gate arrays; median filters; Xilinx XC4010 FPGA chip; algorithm; design; real time median filter; sliding window; Clocks; Design automation; Field programmable gate arrays; Filters; Independent component analysis; Random access memory; Routing; Tellurium; Throughput; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1997. Proceedings., Tenth International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-7755-4
  • Type

    conf

  • DOI
    10.1109/ICVD.1997.568194
  • Filename
    568194
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1962258