DocumentCode
1962438
Title
Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI
Author
Abouzeid, Fady ; Bienfait, Audrey ; Akyel, Kaya Can ; Clerc, Sylvain ; Ciampolini, L. ; Roche, Philippe
Author_Institution
STMicroelectron., Crolles, France
fYear
2013
fDate
16-20 Sept. 2013
Firstpage
205
Lastpage
208
Abstract
We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10× energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.
Keywords
CMOS memory circuits; SRAM chips; integrated circuit yield; silicon-on-insulator; FDSOI technology; Si-CAD correlation; bulk CMOS technology; high yield; minimum voltage prediction; scalable SRAM bitcell design; size 28 nm; size 65 nm; ultrawide voltage range SRAM bitcell array; voltage 0.35 V; voltage 1.2 V; Arrays; Low voltage; Microprocessors; Random access memory; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2013 Proceedings of the
Conference_Location
Bucharest
ISSN
1930-8833
Print_ISBN
978-1-4799-0643-7
Type
conf
DOI
10.1109/ESSCIRC.2013.6649108
Filename
6649108
Link To Document