FPGA implementation of a 1,090 MHz SSR receiving and precision TOA estimation station

In this article the first complete 1,090 MHz SSR receiving and precision time of arrival (TOA) estimation station field programmable gate array (FPGA) implementation and its analog electronic front-end is presented. The station is designed for local area multilateration (LAM), wide area multilateration (WAM) and automatic dependent surveillance-broadcast (ADS-B) systems. Furthermore it´s fully international civil aviation organization (ICAO) annex X volume IV [1], ED-117 [2] and ED-142 [3] compliant. The station consists principally of an antenna, an analog front-end, an analog-to-digital converter (ADC), a FPGA and a system-on-chip (SoC) microcomputer. The secondary surveillance radar (SSR) signals are received with a low loss half-wave vertical dipole antenna, amplified and then down-converted with the analog front-end, digitalized with the ADCs and finally demodulated, decoded and TOA estimated with the FPGA implementation. The microcomputer´s scope is to emit the decoded and TOA estimated SSR signals and its monitoring information over the network to the central processing station (CPS). To achieve high position accuracy the system´s clock reference is locked to an oven controlled crystal oscillator (OCXO) with an optional global position system (GPS) correction. The presented architecture is capable of time stamping with a resolution of 40 ps and an RMS accuracy of 1.5 ns, which corresponds to a distance accuracy of 0.3 m.