• DocumentCode
    1963026
  • Title

    A 0.039mm2 inverter-based 1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC in 65nm CMOS

  • Author

    Zeller, Sebastian ; Muenker, Christian ; Weigel, Robert

  • fYear
    2013
  • fDate
    16-20 Sept. 2013
  • Firstpage
    319
  • Lastpage
    322
  • Abstract
    We propose design techniques for the realization of power- and area-efficient CT-ΣΔ-ADCs in ultra deep submicron CMOS: A resonant single-opamp 3rd order integrator with loss compensation, an inverter-based opamp with digitally-assisted biasing and common mode control, a pseudo-differential modulator topology with quasi-1.5-bit quantization and FIR-DACs with passive DT compensation. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented to prove these concepts. The entire active analog circuitry in this minimalistic 3rd order modulator consists of only 10 CMOS inverters.
  • Keywords
    CMOS integrated circuits; invertors; FIR DAC; active analog circuitry; common mode control; digitally assisted biasing; inverter based opamp; minimalistic 3rd order modulator; passive DT compensation; power 1.82 mW; pseudo differential modulator topology; resonant single opamp; size 65 nm; ultra deep submicron CMOS inverters; voltage 1.1 V; CMOS integrated circuits; Finite impulse response filters; Gain; Inverters; Modulation; Noise; Quantization (signal);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ESSCIRC (ESSCIRC), 2013 Proceedings of the
  • Conference_Location
    Bucharest
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4799-0643-7
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2013.6649137
  • Filename
    6649137
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1963026