DocumentCode
1963280
Title
Hot electron induced punchthrough (HEIP) in p-channel SOI MOSFET´s
Author
Zhao, X. ; Ioannou, D.E. ; Jenkins, W.C. ; Hughes, H.L. ; Liu, S.T.
Author_Institution
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
fYear
1998
fDate
5-8 Oct. 1998
Firstpage
83
Lastpage
84
Abstract
Summary form only given. Due to their paramount importance for the development of high performance and low power/low voltage SOI CMOS technologies, SOI MOSFET short channel effects and subthreshold characteristics have been studied extensively and are now both well understood and fairly well controlled. The same is true for hot carrier effects and reliability of n-channel SOI MOSFETs. However, as with the bulk CMOS case, hot carrier studies of p-channel SOI MOSFETs have lagged behind, with only a few reports available in the open literature (Tsuchiya et al. 1994; Renn et al, 1998). This is rather surprising, since an important hot carrier induced short channel effect, hot electron induced punchthrough (HEIP), has been found to be the worst case condition in predicting the lifetime of bulk p-channel devices (Koyanagi et al. 1987). In this paper an investigation of the HEIP in p-channel SOI MOSFETs is carried out. It is found that, much like the bulk case, hot electron trapping in the gate oxide near the drain causes an effective drain extension, thereby causing a corresponding punchthrough voltage reduction. A logarithmic time dependence of this reduction is observed, in good agreement with a simple one-dimensional analytical model.
Keywords
CMOS integrated circuits; MOSFET; electron traps; hot carriers; semiconductor device models; semiconductor device reliability; semiconductor device testing; silicon-on-insulator; 1D analytical model; HEIP effect; SOI MOSFET short channel effects; SOI MOSFET subthreshold characteristics; Si-SiO/sub 2/; bulk p-channel device lifetime; effective drain extension; gate oxide; hot carrier effects; hot carrier induced short channel effect; hot electron induced punchthrough; hot electron trapping; low power SOI CMOS technology; low voltage SOI CMOS technology; n-channel SOI MOSFETs; p-channel SOI MOSFETs; punchthrough voltage; punchthrough voltage reduction logarithmic time dependence; reliability; Charge carrier processes; Contracts; Hot carrier effects; Hot carriers; IEL; MOSFET circuits; Secondary generated hot electron injection; Stress; Substrate hot electron injection; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location
Stuart, FL, USA
ISSN
1078-621X
Print_ISBN
0-7803-4500-2
Type
conf
DOI
10.1109/SOI.1998.723122
Filename
723122
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