DocumentCode
1963982
Title
A 6b 46GS/s ADC with >23GHz BW and sparkle-code error correction
Author
Yida Duan ; Alon, Elad
Author_Institution
UC Berkeley, Berkeley, CA, USA
fYear
2015
fDate
17-19 June 2015
Abstract
This paper presents a 6b 46GS/s 72-way hierarchically time-interleaved asynchronous SAR ADC utilizing cascode samplers to achieve >23GHz BW. A back-end meta-stability correction circuit enables sparkle-code error-free operation over 1e10 samples. The 28nm FDSOI ADC achieves 27dB SNDR (low frequency)/25.2dB (at 23.5GHz) while consuming 381mW from 1.05V/1.6V supplies and occupies 0.14mm2.
Keywords
analogue-digital conversion; asynchronous circuits; error correction codes; silicon-on-insulator; 1e10 sample; FDSOI ADC; SNDR; back-end metastability correction circuit; cascode sampler; frequency 23.5 GHz; fully depleted silicon-on-insulator; power 381 mW; size 28 nm; sparkle-code error correction; successive approximation analog-digital converter; time-interleaved asynchronous SAR ADC; voltage 1.05 V; voltage 1.6 V; Circuit stability; Clocks; Delays; Detectors; Error-free operations; MOS devices; Time-frequency analysis; ADC; cascode sampler; meta-stability correction; sparkle-codes;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231250
Filename
7231250
Link To Document