A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias

Author

Umemoto, Y. ; Nii, K. ; Ishikawa, J. ; Okamoto, K. ; Mori, K. ; Yanagisawa, K.

Author_Institution

Renesas Electron. Corp., Kodaira, Japan

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

We propose a new 2T mask ROM with dynamic column source bias control technique, which allows us to achieve both high-speed operation and low-power consumption. One can also overcome the inherent problem of the cross-talk noise between bitlines. The fabricated 128-kb ROM macro using 28-nm high-k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at 0.85 V, which is comparable with recent high-speed embedded SRAMs. Measured active power dissipation is 0.5× smaller than conventional 2T ROM. The standby leakage also can be reduced to a half of the conventional macros.

Keywords

CMOS memory circuits; crosstalk; high-k dielectric thin films; integrated circuit noise; read-only storage; active power dissipation; crosstalk noise; dynamic column source bias; high-k dielectric thin films; high-speed embedded SRAM; metal-gate CMOS bulk technology; power reduced 2T mask ROM; read access time; size 28 nm; storage capacity 128 Kbit; time 0.72 ns; voltage 0.85 V; CMOS integrated circuits; CMOS technology; Layout; Noise; Power demand; Random access memory; Read only memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055317

Filename

6055317