Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

Author

Huang, Ru ; Wang, Runsheng ; Zhuge, Jing ; Liu, Changze ; Yu, Tao ; Zhang, Liangliang ; Huang, Xin ; Ai, Yujie ; Zou, Jinbin ; Liu, Yuchao ; Fan, Jiewen ; Liao, Huailin ; Wang, Yangyuan

Author_Institution

Peking Univ., Beijing, China

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

8

Abstract

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

Keywords

MOSFET; nanowires; 1D nanowire-channel device; 3D surrounding gate; Si; carrier transport behavior; circuit co-design; gate-all-around nanowire transistors; hierarchical modeling; parasitic effects; self-heating effect; ultimately scaled CMOS devices; Capacitance; Logic gates; MOSFETs; Nanoscale devices; Noise; Resistance; Resource description framework;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055334

Filename

6055334