FPGA based design of a novel enhanced error detection and correction technique

With the increase of data transmission and hence sources of noise and interference, engineers have been struggling with the demand for more efficient and reliable techniques for detecting and correcting errors in received data. Although several techniques and approaches have been proposed and applied in the last decade, data reliability in transmission is still a problem. In this paper we propose a high efficient combined error detection and correction technique based on the Orthogonal Codes Convolution, Closest Match, and vertical parity. This method has been experimentally implemented and simulated using Field Programmable Gate Array (FPGA). Simulation results show that the proposed technique detects 99.99% of the errors and corrects as predicted up to (n/2-1) bits of errors in the received impaired n-bit code.