An at-speed self-testable technique for the high speed domino adder

Author

Wang, Yu-Shun ; Hsieh, Min-Han ; Liu, Chia-Ming ; Liu, Chi-Wei ; Li, James C M ; Chen, Charlie Chung-Ping

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

An at-speed self-testable technique is proposed for the high speed domino adder. We apply pseudo-exhaustive testing so that all testable faults in the 64-bit adder are detected by just 23K patterns. The adder latency is accurately measured by the programmable-skew clock generated from delay-locked loop (DLL). The proposed technique is validated on a 6.4GHz 64-bit domino adder with 181ps latency in 90nm CMOS technology. This on-chip technique is very useful for at-speed testing and speed binning of high performance CPU.

Keywords

CMOS digital integrated circuits; adders; integrated circuit testing; CMOS technology; adder latency; at-speed self-testable technique; delay-locked loop; frequency 6.4 GHz; high speed domino adder; programmable-skew clock; pseudo-exhaustive testing; size 90 nm; word length 64 bit; Adders; CMOS integrated circuits; Circuit faults; Clocks; Generators; Measurement techniques; Testing; LFSR; at-speed self test; delay lock loop (DLL); domino adder; latency; pseudo-exhaustive testing; speed binning;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055417

Filename

6055417