A CMOS quaternary threshold logic full adder circuit with transparent latch

A circuit that realizes the quaternary threshold logic full adder function with transparent latching has been realized in a standard polysilicon-gate CMOS technology. In its FOLLOW mode, the quaternary full adder accepts two quaternary inputs and a binary CARRY input, and develops a two-quaternary-digit output word that is the base-four sum of the inputs. In the HOLD mode, these output states are held by the transparent multiple-valued latch subcircuit. The circuit is presented and its experimental performance described