Chip level reliability on SOI embedded memory

In modern DRAM products, stacked-capacitor (STC) cells are widely utilized because the STC cell structure has the advantage of easy fabrication of the storage capacitors. Meanwhile, the drawback of STC cells is the increasing difficulty of the back-end process with each DRAM generation due to the high contact hole aspect ratio resulting from the step height difference between the peripheral circuit regimes and memory array regimes. This paper describes a novel stacked-capacitor cell structure with a simple wiring process which utilizes the virtual flat surface at the bottom of SOI stacked-capacitor cells. The virtual flat surface is made into a real surface by reversing the capacitor and polishing the substrate with bonded-SOI technology (Nishihara et al. 1992). This memory cell is named an embedded memory SOI process (EMSP)(Kim et al. 1996). In this paper, we analyze the problems of capacitor formation under an SOI structure, and confirm the process limitations to improve the embedded memory SOI process, using a 16 Mb SOI DRAM with 0.35 /spl mu/m design rule technology. We have previously reported the basic EMSP. We focus here on chip-level reliability issues for EMSP memory cell structures and present some solutions.