Advanced circuit techniques for high-performance microprocessor and low-power DSPs

Author

Mathew, Sanu ; Krishnamurthy, Ram ; Anders, Mark ; Hsu, Steven ; Borkar, Shekhar

Author_Institution

Circuit Res., Intel Labs, Intel Corp., Hilisboro, OR, USA

fYear

2004

fDate

27 Sept. 2004

Firstpage

1

Lastpage

45

Abstract

This article presents the challenges and solutions for a high-performance microprocessors and low-power digital signal processing chips. It discusses the high-performance power-efficient execution core such as the 6.5 GHz single-rail domino 32-bit Han-Car ALU; the 4 GHz semi-dynamic 32-bit sparse-tree AGU. It also deals with leakage-tolerant register files; conditional/burn-in keeper; pseudo-static bitlines; low-power datapaths for DSP applications; and the 1 GHz 16-bit static multiplier.

Keywords

current limiters; digital arithmetic; digital signal processing chips; integrated circuit design; low-power electronics; multiplying circuits; 1 GHz; 16 bits; 32 bits; 4 GHz; 6.5 GHz; DSP applications; Han-Car ALU; advanced circuit techniques; conditional/burn-in keeper; digital signal processing chips; high-performance microprocessor; high-performance power-efficient execution core; leakage-tolerant register files; low-power DSP; low-power datapaths; pseudostatic bitlines; semidynamic sparse-tree AGU; single-rail domino; static multiplier; Current limiters; Digital arithmetic; Digital signal processors; Integrated circuit design; Multiplying circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Implementation of High Performance Circuits, 2004. (DCAS-04). Proceedings of the 2004 IEEE Dallas/CAS Workshop

Print_ISBN

0-7803-8713-9

Type

conf

DOI

10.1109/DCAS.2004.1360432

Filename

1360432