SPHIR-a system for parallel hierarchical routing

The possibility of a routing accelerator for VLSI routing based on general-purpose processors and a general-purpose architecture which can be used to speed up other phases of the VLSI design cycle is investigated. Research into a novel technique for exploiting parallelism in the automatic routing process for hierarchical VLSI circuit design is presented. The routing tools are incorporated into a routing system which can be used to exploit parallelism in the routing process whilst making the fullest use of the structural hierarchy of the VLSI layout. In VLSI design routing is performed in two stages: loose routing followed by detailed routing. The model clearly identifies where parallelism can be best exploited in each of these stages