Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic

Author

Ciric, Jovanka ; Yee, Gin ; Sechen, Carl

Author_Institution

Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA

fYear

2000

fDate

2000

Firstpage

277

Lastpage

282

Abstract

This paper presents a new delay minimization and technology mapping algorithm for two-level structures (TLS) implemented using clock-delayed (CD) domino logic. We take advantage of CD domino´s high-speed, large fan-in NOR and OR gates to increase the speed of a circuit by partial collapsing. The algorithm is delay-driven and the delays are obtained from a characterized CD domino library. The results on eight combinational MCNC benchmark circuits show an average speed improvement of 89% for CD domino with TLS, compared to static CMOS implementations generated by Synopsys. CD domino with TLS using our tools produced on average 44% faster circuits than CD domino benchmarks minimized and mapped using Synopsys. The delay results for CD domino with TLS were on average 22% better than for standard domino

Keywords

clocks; delays; logic CAD; logic gates; logic partitioning; minimisation of switching nets; clock-delayed domino logic; delay minimization; fan-in; partial collapsing; speed improvement; technology mapping; two-level structures; Automatic logic units; CMOS logic circuits; Circuit synthesis; Clocks; Clustering algorithms; Delay; Logic circuits; Logic design; Logic devices; Minimization methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings

Conference_Location

Paris

Print_ISBN

0-7695-0537-6

Type

conf

DOI

10.1109/DATE.2000.840284

Filename

840284