An improved min-net-cut approach for gate-matrix and metal-metal matrix circuit layout

An algorithm to minimize the number of tracks, and hence the layout area, for gate-matrix and metal-metal-matrix layouts is presented. Unlike traditional algorithms, which minimize the layout area by minimizing the net-density between columns, the algorithm minimizes the net-density across the columns of a layout. The gate-matrix and the metal-metal matrix layout optimization problem are discussed, followed by a short discussion on the deficiencies of the traditional min-net-cut-based column ordering algorithms. The authors´ algorithm for minimizing the layout area is presented. This approach and the traditional min-net-cut-based approach for metal-metal matrix layouts are compared