Body-bias compensation technique for subthreshold CMOS static logic gates

Author

Melek, Luiz Alberto P ; Schneider, Marcio C. ; Galup-Montoro, Carlos

Author_Institution

Univ. Fed. de Santa Catarina, Florianopolis, Brazil

fYear

2004

fDate

7-11 Sept. 2004

Firstpage

267

Lastpage

272

Abstract

This paper analyzes the performance of the conventional CMOS inverter, NAND-2 and NOR-2 static logic gates operating in the subthreshold region. The dependence of the drain currents on the process parameters can give rise to drive currents of NMOS and PMOS transistors that differ by an order of magnitude or even more. To compensate for this difference in currents, we propose three bias circuits in single-well processes that adjust the body voltage. Computer simulations using the AMS 0.8 μm technology and the BSIM3v3 model were carried out to assess the compensation technique. A test chip was fabricated in both AMIS 1.5 μm and TSMC0.35 μm to further validate the proposal.

Keywords

CMOS logic circuits; MOSFET; compensation; digital simulation; invertors; logic gates; 0.35 micron; 0.8 micron; 1.5 micron; AMIS technology; AMS technology; BSIM3v3 model; CMOS inverter; NAND-2 gate; NMOS transistor; NOR-2 static logic gates; PMOS transistors; bias circuits; body bias compensation technique; computer simulations; drain currents; subthreshold CMOS static logic gates; CMOS logic circuits; CMOS technology; Circuit testing; Computer simulation; Logic gates; MOS devices; MOSFETs; Performance analysis; Pulse inverters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on

Print_ISBN

1-58113-947-0

Type

conf

DOI

10.1109/SBCCI.2004.240981

Filename

1360582