Device degradation models for circuit reliability simulation

With reliability margins shrinking, it is increasingly important to carefully assess the impact of device degradation during circuit design. Circuit reliability simulation is a very useful tool for this purpose as it allows designers to guarantee that circuits are sufficiently robust against device degradation, while they are not bound by overly robust design rules. Hence its usage is becoming more and more widely adopted in mixed signal circuit design. Various degradation mechanisms can be evaluated using circuit reliability simulation including hot carrier degradation, NBTI, PBTI as well as TDDB. In this paper I will present the underlying models that are available to describe device degradation as a function of stress conditions. I will explain the methodology used for translating DC degradation models to the time varying stress signals encountered in actual circuits as well as the justification and the limitations of adopting this approach. I will discuss standard CMOS as well as bipolar and DMOS transistors.