Multiprocessor DSP scheduling in system-on-a-chip architectures

Next generation embedded systems will demand applications with increasing complexity, so a standard uniprocessor microcontroller architecture will likely be unsuited to support. A possible solution to cope with embedded applications with high computational requirements is to adopt multiple-processor-on-a-chip architectures. The paper discusses the problem of multiprocessor scheduling for asymmetric architectures composed of a general purpose CPU and a DSP. The challenging issue addressed in this work is to verify whether the use of a dedicated processor can effectively enhance the performance of an embedded system, still maintaining some kind of real-time guarantee. In particular, we provide a method for increasing the schedulability bound in the considered architecture, allowing a more efficient use of the computational resources.