DocumentCode
1974148
Title
A novel load balancing method for multi-core with non-uniform memory architecture
Author
Ahn, Youngho ; Kim, Sea-Ho ; Chung, Ki-Seok ; Kim, Won-Jin ; Kim, Hi-Seok ; Han, Tae Hee
Author_Institution
Dept. of Electron., Comput. & Commun. Eng., Hanyang Univ., Seoul, South Korea
fYear
2010
fDate
22-23 Nov. 2010
Firstpage
412
Lastpage
415
Abstract
As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program effectively in a distributed fashion on asymmetric memory architecture is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade-off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods.
Keywords
distributed memory systems; memory architecture; probability; resource allocation; asymmetric memory architecture; distributed memory architecture; load balancing effect; load balancing method; multicore systems; nonuniform memory architecture; probabilistic information; Automatic voltage control; Decoding; High definition video; Load management; Memory architecture; Multicore processing; NUMA; bebavior pattern analysis; load balancing; multi-core; parallel;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2010 International
Conference_Location
Seoul
Print_ISBN
978-1-4244-8633-5
Type
conf
DOI
10.1109/SOCDC.2010.5682884
Filename
5682884
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