DocumentCode
1976391
Title
Package design for high-speed SerDes
Author
Young, Brian ; Bhandal, Amarjit S.
Author_Institution
ASIC Package Design, Texas Instrum., Austin, TX, USA
fYear
2010
fDate
7-9 Dec. 2010
Firstpage
1
Lastpage
4
Abstract
High-speed SerDes signals are significantly distorted by the time they leave the package. The distortion is caused by excess capacitive loading at points along the signal path, causing reflections. The reflections can be minimized through design modifications, added structures for compensation, filters, and characteristic impedance shifts.
Keywords
capacitance; distortion; electric impedance; electronics packaging; filters; high-speed techniques; transmission lines; capacitive loading; compensation; filter; high-speed SerDes signal; impedance shift; package design; signal distortion; Capacitance; Electronics packaging; Impedance; Inductance; Power transmission lines; Reflection; Tuning;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE
Conference_Location
Singapore
ISSN
2151-1225
Print_ISBN
978-1-4244-9068-4
Electronic_ISBN
2151-1225
Type
conf
DOI
10.1109/EDAPS.2010.5682990
Filename
5682990
Link To Document