Effect of ground plane design for WLP with signal integrity modeling and analysis

Author

Siew, Glen ; Yan, Tee Tong ; Haoyang, Chen ; Soh, Serine ; Heon, Kim Jong

Author_Institution

R&D Team, Nepes Pte Ltd., Singapore, Singapore

fYear

2010

fDate

7-9 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

Analysis of ground plane design effect for Wafer Level Package (WLP) through advance electrical modeling and simulation for chip-package-board signal integrity co-design was carried out. Increase in information transfer rates is greatly limited by bandwidth of communication channel at PCB board receiver due to channel loss, signal cross-talk, and signal distortion which are critical factors affecting signal integrity of channel and high-speed links such as LVDS, SSTL, LVTTL, LVCMOS and PCI-X. In this work, ground plane design approaches of 2 metal-layer WLP were studied to enhance the signal margin of high-speed signals.

Keywords

chip-on-board packaging; crosstalk; distortion; printed circuits; wafer level packaging; LVCMOS; LVDS; LVTTL; PCB board receiver; PCI-X; SSTL; advance electrical modeling; channel loss; chip-package-board signal integrity codesign simulation; communication channel; ground plane design effect; high-speed links; high-speed signals; metal-layer WLP; signal crosstalk; signal distortion; signal integrity modeling; wafer level package;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE

Conference_Location

Singapore

ISSN

2151-1225

Print_ISBN

978-1-4244-9068-4

Electronic_ISBN

2151-1225

Type

conf

DOI

10.1109/EDAPS.2010.5682993

Filename

5682993