Evaluation of parasitic capacitance introduced during tag assembly process

Power transfer between tag chip and tag antenna plays a critical role in determining the performance of passive UHF RFID systems. However, optimum power transfer is difficult to achieve due to parasitic capacitance introduced during the tag assembly process. Moreover, the parasitic capacitance leads to performance deviation and tag detuning. Thus it is highly desired to determine the parasitic capacitance before initializing tag antenna design. This paper presents a fast and quantitative method to evaluate the parasitic capacitance. The method is established based on a lumped-element model of double-tuned tags and the corresponding expression of the power transfer coefficient. Simulation and measurement results are provided to verify the proposed method. For strap-packaged Alien Higgs-3 chip and embedded T-match antenna assembled with an anisotropic conductive adhesive, the parasitic capacitance is demonstrated to be about 0.265-0.321 pF.