Distributed arithmetic in the design of high speed hardware fuzzy inference systems

Author

Gaona, Andrés ; Olea, David ; Melgarejo, Miguel

Author_Institution

Lab. for Autom., Microelectron. & Comput. Intelligence, Univ. Distrital Francisco Jose de Caldas, Colombia, SC, USA

fYear

2003

fDate

24-26 July 2003

Firstpage

116

Lastpage

120

Abstract

This paper presents an approach for implementing center average defuzzifier by means of distributed arithmetic. This approach was applied in the design of two digital fuzzy processors, their architectures are described and compared in terms of system level organization. An automatic hardware code generation tool was used for specifying these fuzzy processors. Furthermore, they were implemented over a VirtexE® FPGA. Implementation results show that it is possible to obtain a processing speed up to 45 MFLIPS and reduced area cost for distributed arithmetic based parallel organized fuzzy inference systems.

Keywords

distributed arithmetic; fuzzy systems; inference mechanisms; parallel architectures; program compilers; HFIS; VirtexE® FPGA; automatic hardware code generation tool; center average defuzzifier; digital fuzzy processors; distributed arithmetic; field programmable gate arrays; hardware based fuzzy inference systems; parallel architectures; parallel organized fuzzy inference systems; processing speed; system level organization; Arithmetic; Automation; Computer architecture; Engines; Field programmable gate arrays; Fuzzy sets; Fuzzy systems; Hardware; Laboratories; Microelectronics;

fLanguage

English

Publisher

ieee

Conference_Titel

Fuzzy Information Processing Society, 2003. NAFIPS 2003. 22nd International Conference of the North American

Print_ISBN

0-7803-7918-7

Type

conf

DOI

10.1109/NAFIPS.2003.1226766

Filename

1226766