28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder

Author

Abouzeid, Fady ; Clerc, Sylvain ; Pelloux-Prayer, Bertrand ; Argoud, Fabrice ; Roche, Philippe

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

17-21 Sept. 2012

Firstpage

153

Lastpage

156

Abstract

A minimum design effort methodology to enable energy efficient and variability tolerant ultra-wide voltage-range frame error-decoder design in 28nm CMOS technology is presented. Critical aspects of a digital design development - standard cells, interface, clock tree and implementation - were optimized enabling 1.0V to 350mV functionality, 10x energy reduction, 10MHz to 700MHz frequency, and a reduction of the variability enabling industrial yield at ultra-low voltage. The same design was then ported to 28nm Fully-Depleted SOI (FDSOI), offering up-to 2x higher energy efficiency while validating the design methodology robustness.

Keywords

CMOS integrated circuits; decoding; integrated circuit design; silicon-on-insulator; CMOS technology; FDSOI; Si; clock tree; digital design development; energy reduction; frequency 10 MHz to 700 MHz; fully-depleted SOI; size 28 nm; standard cell; ultrawide voltage-range frame error-decoder; voltage 350 mV to 1.0 V; word length 252 bit; CMOS integrated circuits; CMOS technology; Clocks; Delay; Libraries; Silicon; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2012 Proceedings of the

Conference_Location

Bordeaux

ISSN

1930-8833

Print_ISBN

978-1-4673-2212-6

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2012.6341282

Filename

6341282