DocumentCode
1980120
Title
Compact model of MOSFET electron tunneling current through ultra-thin SiO/sub 2/ and high-k gate stacks
Author
Fei Li ; Mudanai, S.P. ; Yang-Yu Fan ; Register, L.F. ; Banerjee, S.K.
Author_Institution
Microelectron. Res. Center, Texas Univ., Austin, TX, USA
fYear
2003
fDate
23-25 June 2003
Firstpage
47
Lastpage
48
Abstract
In this paper, we present an accurate, physics-based compact modeling tool for tunneling current through ultra-thin gate dielectrics including high-k gate stacks. This work extends our previous work on physics-based compact modeling of the CV of ultrathin oxides.
Keywords
MOSFET; WKB calculations; dielectric materials; dielectric thin films; semiconductor device models; silicon compounds; tunnelling; MOSFET; SiO/sub 2/; electron tunneling current; gate stacks; ultra-thin SiO/sub 2/; Charge carrier processes; Computational modeling; Electrons; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFET circuits; Predictive models; Quantum computing; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference, 2003
Conference_Location
Salt Lake City, UT, USA
Print_ISBN
0-7803-7727-3
Type
conf
DOI
10.1109/DRC.2003.1226865
Filename
1226865
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