A 0.024 mm² 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

Author

Yin, Guohe ; Wei, He-Gong ; Chio, U-Fat ; Sin, Sai-Weng ; Seng-Pan, U. ; Wang, Zhihua ; Martins, Rui Paulo

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2012

fDate

17-21 Sept. 2012

Firstpage

377

Lastpage

380

Abstract

This paper presents a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design for sensor applications. An energy-saving switching technique is proposed to achieve ultra low power consumption. The measured Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is 58.4 dB at 2 MS/s with an ultra-low power consumption of only 6.6 μW from a 0.8V supply, resulting in a Figure-Of-Merit (FOM) of 4.9 fJ/conversion-step. The prototype is fabricated in 65 nm CMOS technology with an area of 0.024 mm².

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit noise; low-power electronics; sensors; CMOS; SAR ADC; energy-saving switching technique; figure-of-merit; power 6.6 muW; sensor application; signal-to-noise-and-distortion ratio; size 65 nm; successive approximation register analog-to-digital converter design; ultra low power consumption; voltage 0.8 V; word length 10 bit; Approximation methods; Arrays; CMOS integrated circuits; Capacitance; Capacitors; Registers; Switches; Analgo-to-Digital converter; Successive Approximation Register; sensor applications; ultra-low power;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2012 Proceedings of the

Conference_Location

Bordeaux

ISSN

1930-8833

Print_ISBN

978-1-4673-2212-6

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2012.6341364

Filename

6341364

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

Yin, Guohe ; Wei, He-Gong ; Chio, U-Fat ; Sin, Sai-Weng ; Seng-Pan, U. ; Wang, Zhihua ; Martins, Rui Paulo

conf

A 0.024 mm² 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS