Electron transport through accumulation layers and its effect on the series resistance of MOS transistors

Author

Gutierrez-D, E.A.

Author_Institution

INAOE, Puebla

fYear

1998

fDate

2-4 Mar 1998

Firstpage

51

Lastpage

54

Abstract

A theoretical and experimental study of electron conduction through an electron-accumulated region is presented. The model developed to study carrier conduction through accumulation layers is validated with experimental results obtained from test structures fabricated in two different 0.7 μm CMOS technologies. The results obtained here are generalized and extended to explain the gate-voltage dependence of the series resistance of MOS transistors

Keywords

MOSFET; accumulation layers; electric resistance; semiconductor device measurement; semiconductor device models; surface potential; 0.7 mum; C-V characteristics; CMOS technologies; I-V characteristics; MOS transistors; accumulation layer electron transport; carrier conduction; drain current; electron-accumulated region; gate-voltage dependence; model; series resistance; surface potential; test structures; transconductance; Astrophysics; CMOS technology; Doping; Electric resistance; Electron optics; MOSFET circuits; Resistors; Semiconductor device modeling; Testing; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference on

Conference_Location

Isla de Margarita

Print_ISBN

0-7803-4434-0

Type

conf

DOI

10.1109/ICCDCS.1998.705804

Filename

705804