Wideband Circuit Model of Silicon-Based Interconnects Up to 50 GHz

Author

Luo, Gang ; Yin, Wen-Yan ; Kang, Kai ; Shi, Jing-Lin ; Xie, Jian-Yong ; Mao, Jun-Fa

Author_Institution

Sch. of Electron. Inf. & Electr. Eng., Shanghai Jiao Tong Univ., Shanghai

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

1

Lastpage

4

Abstract

This paper presents a wideband circuit model of silicon-based interconnects for predicting their metallic and silicon substrate losses at higher frequencies. The skin and proximity effects in the structure are characterized using the partial element equivalent circuit (PEEC) method, and the parasitic parameters in silicon substrate are captured according to some analytical equations. Good agreements are obtained between the measurement and simulated data up to 50 GHz, with the interconnect samples fabricated using 0.18 um CMOS process.

Keywords

CMOS integrated circuits; equivalent circuits; integrated circuit interconnections; CMOS process; frequency 50 GHz; metallic substrate loss; parasitic parameters; partial element equivalent circuit method; proximity effect; silicon substrate loss; silicon-based interconnects; skin effect; wideband circuit model; Circuit simulation; Equations; Equivalent circuits; Frequency; Integrated circuit interconnections; Predictive models; Proximity effect; Silicon; Skin; Wideband; interconnects; lumped-element circuit model; metallic loss; partial element equivalent circuit (PEEC); substrate loss;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2007. APMC 2007. Asia-Pacific

Conference_Location

Bangkok

Print_ISBN

978-1-4244-0748-4

Electronic_ISBN

978-1-4244-0749-1

Type

conf

DOI

10.1109/APMC.2007.4555062

Filename

4555062