Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations

Because of the increasing complexity of modern embedded systems, High-Level Synthesis (HLS) has gained momentum. Most HLS tools employ Control Data Flow Graph (CDFG) based approaches. An alternative route from C to RTL was presented in [1], where a CDFG based approach was augmented with a polyhedral process networkbased approach. This alternative route enables application of high-level transformations giving a significant increase in utilization of pipelined components, which positively affects throughput. However, increased pipeline utilization could be obtained only after manuallyselecting a set of transformations to apply, which is a non-trivial task.The main contribution of this paper is a reordering buffer that enablesautomatic improvement of pipeline utilization.