VLSI design of an algebraic-integer signal processor

Author

Games, Richard A. ; Moulin, Daniel ; Rushanan, Joseph J.

Author_Institution

MITRE Corp., Bedford, MA, USA

fYear

1989

fDate

14-16 Aug 1989

Firstpage

808

Abstract

A programmable 128-tap linear systolic FIR filter was implemented in VLSI with a throughput of 5 MHz. The design combines algebraic-integer quantization and residue number system (RNS) processing in order to add a second level of parallelism to integer RNS processing, generalizing the quadratic RNS concept. This 9-b processor performs equivalently to an integer processor with 20 b of dynamic range

Keywords

VLSI; digital filters; digital signal processing chips; 9 bits; VLSI design; algebraic-integer quantization; algebraic-integer signal processor; integer RNS processing; programmable 128-tap linear systolic FIR filter; residue number system; throughput; Communication switching; Dynamic range; Finite impulse response filter; Quantization; Real time systems; Sensor systems; Signal design; Signal processing; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on

Conference_Location

Champaign, IL

Type

conf

DOI

10.1109/MWSCAS.1989.101978

Filename

101978

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1984448