A digital correction technique for channel mismatch in TI ΣΔ ADCs

Time interleaved sigma-delta analog to digital converter seems to be a potential solution for wide bandwidth analog to digital converter with the lowest hardware complexity compared to other solutions using parallel sigma-delta modulators. Its performance depends on the digital filter and is very sensitive to the channel mismatch. This paper summarizes our work on the digital signal processing for this kind of converter, including filtering, decimation and channel mismatch correction in order to reduce the implementation complexity while minimizing the channel mismatch effect.