GMICRO/500 microprocessor: pipeline structure of superscalar architecture

Author

Yamamoto, Manabu ; Kawasaki, Issei ; Narita, S. ; Arakawa, Fumio ; Uchiyama, Kenji

fYear

1992

fDate

2-4 Dec 1992

Firstpage

56

Lastpage

62

Abstract

The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed, illustrating the effect of a pipe bypass mechanism and dedicated resident branch instruction caches. The benefit of microprogram-controlled instruction execution for high-speed execution of high-level language instructions is shown. Overall GMICRO/500 performance is evaluated in Dhrystones

Keywords

microprogramming; parallel architectures; pipeline processing; 32 bit; 5-stage dual-pipeline superscalar architecture; Dhrystones; GMICRO/500 pipelined instruction execution mechanism; TRON specification; basic instruction execution timing; dedicated resident branch instruction caches; high-level language instructions; microprogram-controlled instruction execution; pipe bypass mechanism; Decoding; Frequency; Gold; High level languages; Laboratories; Microcomputers; Microprocessors; Pipelines; Prefetching; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

TRON Project Symposium, 1992. Proceedings., Ninth

Conference_Location

Tokyo

ISSN

1063-6749

Print_ISBN

0-8186-2990-8

Type

conf

DOI

10.1109/TRON.1992.313268

Filename

313268