DocumentCode
1987876
Title
Double patterning: Simulating a variability challenge for advanced transistors
Author
Evanschitzky, P. ; Burenkov, Alex ; Lorenz, Juergen
Author_Institution
Fraunhofer Inst. for Integrated Syst. & Device Technol. IISB, Erlangen, Germany
fYear
2013
fDate
3-5 Sept. 2013
Firstpage
105
Lastpage
108
Abstract
In this paper a comprehensive study of the impact of variations resulting from double patterning lithography on SRAM performance is presented. In double patterning, feature sizes are reduced by splitting one mask level into two. Besides the increase of process complexity and costs a further penalty is the introduction of uncorrelated variations between the two incremental lithography steps employed.
Keywords
SRAM chips; lithography; SRAM performance; advanced transistors; double patterning lithography; feature sizes; incremental lithography steps; mask level; process complexity; uncorrelated variations; variability challenge; Computational modeling; Lighting; Lithography; Logic gates; Random access memory; Resists; Transistors; 20nm gate length; Photo lithography; SOI CMOSFETs; SRAM; double patterning;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on
Conference_Location
Glasgow
ISSN
1946-1569
Print_ISBN
978-1-4673-5733-3
Type
conf
DOI
10.1109/SISPAD.2013.6650585
Filename
6650585
Link To Document