Counteracting power analysis attack using Static Single-ended Logic

Dynamic and Differential Logics (DDLs) used for providing resistance against power analysis consume significant area. In order to tackle the area cost this paper examines using a Static and Single-ended Logic (SSL) for designing gates and registers which are resistant against power analysis. Current-Balanced Logic (CBL) is chosen and an empirical analysis is conducted for evaluating the effectiveness of CBL in a test chip fabricated in 0.18μm CMOS process. The increased resistance obtained by CBL requires significantly less area than the previously reported logic level countermeasures. No complex layout methodology as the one used for DDL is needed for implementation of CBL. The results presented in this paper are important for providing resistance against power analysis for area-constrained applications with no battery operated supply.