Design and analysis of a switched-capacitor-based peak detector

In this paper, a CMOS peak detector is proposed. The proposed peak detection is based on signal´s slope variation and it can be easily exploited for positive as well as negative peak detection. Besides it can also be used for multiple peak detection without needing resetting operation, making the circuit implementation quite simple. A switched-capacitor-based (SC-based) implementation is given along with performance analysis based on functional as well as analytical model. The developed analysis gives an insight into the potential performance as well as a design guide to reach the desired target. To have a relative error less than 1 %, the frequency ratio of sampling signal to input signal should be over 22. The proposed peak detector´s operation is confirmed by experimental results from Anadigm FPAA developing board.