A cached system architecture dedicated for the system IO activity on a CPU board

The architecture of a cached IO subsystem on a CPU board of a high-performance workstation is described. The cached IO subsystem is intended to reduce the memory latency for IO activity and minimize the number of processor cycles stolen by IO traffic, to achieve a better balanced computer system in terms of both the CPU computation power and the system IO bandwidth. The model of the cached IO subsystem is shown to illustrate the system architecture. The discussion covers arbitration of system IO activity, the architecture of the virtual address accessed IO cache, the cache coherency algorithm, as well as the comparison of theoretical bounds of IO bandwidth and CPU degradation between different caching schemes