Flexible hardware encoding schemes for extended quasi-cyclic low-density parity-check codes

In this paper, extending technique is employed to quasi-cyclic low-density parity-check (QC-LDPC) codes to construct lower-rate codes from a higher-rate mother code since quasi-cyclic codes can be encoded with simple shift registers, with linear complexity based on their generators. We also present the fitting flexible hardware encoding schemes designed for extended QC-LDPC codes. In the serial-input case and parallel-input parallel-output case, the required maximum encoding circuits which are demanded at the lowest rate are adopted as practical encoder implementation for all of the extended QC-LDPC codes in a sequence and part of hardware units is disabled during higher-rate encoding to reduce power consumption, whereas the hardware circuits are the simplest and totally invariable for a sequence of extended QC-LDPC codes in the parallel-input serial-output case.