A 145µW 8×8 parallel multiplier based on optimized bypassing architecture

Author

Hong, Sunjoo ; Roh, Taehwan ; Yoo, Hoi-Jun

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea

fYear

2011

fDate

15-18 May 2011

Firstpage

1175

Lastpage

1178

Abstract

A low-power parallel multiplier based on optimized bypassing architecture (OBA) is proposed. The proposed OBA has two kinds of adder cells to reduce power consumption by 15.7 %. One is the two-dimensional bypassing adder (TDBA) which performs both row and column bypassing scheme simultaneously, and the other is the modified row-bypassing adder (MRBA) for the proposed row-bypassing scheme. In the proposed TDBA and MRBA, the logic evaluation is partially activated by internal tri-state buffers (ITBs) in order to save the switching power dissipation up to 33.7 % and 32.0 %, respectively. Implemented in 0.13 μm CMOS process, the proposed 8x8 parallel multiplier consumes only 145 μW.

Keywords

adders; low-power electronics; photomultipliers; adder cells; internal tri state buffers; low power; optimized bypassing architecture; parallel multiplier; row bypassing scheme; two dimensional bypassing adder; Adders; CMOS process; Computer architecture; Inverters; Logic gates; Power demand; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5937778

Filename

5937778