Binary signed digit adder design with error detection capability

Binary Signed Digit Number (BSDN) representation has been used to form constant time adders and high-speed multipliers due to the capability of carry-free addition and regular VLSI layout. In order to use that numbering system BSDN digit needs to be encoded into binary bits. One of the possible encoding schemes is the 1-out-of-3 encoding which is a subset of the m-out-of-n codes widely used for error detection and correction. In this work, the design of BSDN full adder cell using the 1-out-of-3 encoding with and without error detection capability is presented. Synthesis results showed that the constant delay feature of the BSDN adder is preserved in both cases. It also showed that the overall performance (delay, area and power) of BSDN adder depends on the effectiveness of the BSDN full adder used to construct it and the desired level of error detection capability.