An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

PRISM, a computer architecture consisting of a general-purpose core processor and a reconfigurable FPGA platform, was designed to bridge the gap between general-purpose and specialized computers. The proof-of-concept system, PRISM-I suffers from several limitations, principal among them being: single bus-cycle restriction on the evaluation time of the function synthesized on an FPGA, inability to execute loops with dynamic loop-counts, and inefficient execution of control constructs such as “if-then-else”. This paper presents a novel execution model in PRISM-II, that addresses the above limitations in a general manner. Also presented is a new framework for translating a C function into an PPGA-based custom architecture