A fast locking DLL clock synthesizer

Author

Choi, Young-Shig ; Choi, Hyuk-Hwan ; Kwon, Tae-Ha

Author_Institution

Div. of Electron., Comput. & Telecommun. Eng., Pukyong Nat. Univ., Busan, South Korea

fYear

2005

fDate

26 June-2 July 2005

Firstpage

830

Lastpage

833

Abstract

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. The DLL has several inherent advantages, such as no jitter accumulation, fast locking and easy integration of the loop filter. This paper proposes a new programmable DKK that includes a new PFD (phase frequency detector) and a new VCDL (voltage controlled delay line) to generate multiple clicks. It can generate clocks from 3 to 10 times of input clock with 5μs locking time. The HSPICE simulation with 0.35μm CMOS process verifies the proposed DLL operating in the frequency range of 300 MHz to 1 GHz.

Keywords

CMOS integrated circuits; UHF integrated circuits; clocks; delay lines; delay lock loops; frequency synthesizers; jitter; programmable circuits; timing circuits; 0.3 to 1 GHz; 0.35 micron; fast locking DLL clock synthesizer; frequency multiplication; jitter accumulation; loop filter; phase frequency detector; programmable delay locked loop; voltage controlled delay line; Clocks; Delay; Filters; Frequency conversion; Jitter; Phase frequency detector; Phase locked loops; Synthesizers; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Science and Technology, 2005. KORUS 2005. Proceedings. The 9th Russian-Korean International Symposium on

Print_ISBN

0-7803-8943-3

Type

conf

DOI

10.1109/KORUS.2005.1507915

Filename

1507915