DocumentCode
1992854
Title
Modeling load address behaviour through recurrences
Author
Ramos, L. ; Ibánez, P. ; Viñals, V. ; Llabería, J.M.
Author_Institution
Dept. Inf. e Ingenieria de Sistemas, Zaragoza Univ., Spain
fYear
2000
fDate
2000
Firstpage
101
Lastpage
108
Abstract
Addresses of load instructions exhibit regularity in their behaviour which is modelled through several models (locality repetitive patterns, etc.) and exploited in processor and memory hierarchy design. Nevertheless, sparse and symbolic applications are intensive in addressing patterns not entirely covered by current models. In this work we introduce a new recurrence among load pairs called “linear link” in order to identify more regularity from such applications. A linear link is a type of recurrence between the value read by a (producer) load and the address issued by a (consumer) load, which is detected tracking on-the-fly dependencies among loads. We consider a broad workload (Nas, Olden, Perfect, Spec95 and IAbench) and conclude that linear links together with stride recurrences can identify many address streams in symbolic and scientific applications traversing either dense, linked data structures or compressed forms of sparse arrays. The two recurrence combinations identify more than 90% of the addresses in more than a half the programs (in 24 our of 55), and more than 75% of the addresses in 90% of the programs (50 our of 55). Finally, we show several measures related to the use of linear links as address predictors for executing loads speculatively and for issuing data prefetches (prediction distance ahead capacity, etc.)
Keywords
data structures; address predictor; address streams; compressed sparse arrays; data prefetches; dense linked data structures; linear link; load address behaviour modelling; load instruction; memory hierarchy design; processor hierarchy design; recurrences; scientific applications; sparse applications; symbolic applications; Data structures; Delay; Ear; High level languages; Instruction sets; Load modeling; Out of order; Proposals; Reduced instruction set computing; Statistics;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance Analysis of Systems and Software, 2000. ISPASS. 2000 IEEE International Symposium on
Conference_Location
Austin, TX
Print_ISBN
0-7803-6418-X
Type
conf
DOI
10.1109/ISPASS.2000.842288
Filename
842288
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