Highly linear current-controlled delay unit

Author

Ahamed, M.R. ; Sandhu, T.S. ; El-Sankary, K.

Author_Institution

Dept. of Electr. & Comput. Eng., Dalhousie Univ., Halifax, NS, Canada

Volume

51

Issue

15

fYear

2015

fDate

7 23 2015

Firstpage

1157

Lastpage

1159

Abstract

A highly linear current-controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/output relation compared with an inversely proportional one in the traditional current-starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue-time-digital ADC is simulated using the proposed CCDU as a front-end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.

Keywords

CMOS integrated circuits; Monte Carlo methods; active networks; delay circuits; invertors; time-digital conversion; CCDU; CMOS; CSI; ENOB; Monte Carlo; THD; analogue-time-digital ADC; current 180 nA; current-starved inverter; directly proportional input-output relation; highly linear current-controlled delay unit; input clock edge; power 0.74 muW; size 65 nm;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2015.1836

Filename

7163404