DocumentCode
1997639
Title
A Reliable Architecture for the Advanced Encryption Standard
Author
Natale, G. Di ; Doulcier, M. ; Flottes, M.L. ; Rouzeyre, B.
Author_Institution
Lab. d´´Inf., Univ. Montpellier II, Montpellier
fYear
2008
fDate
25-29 May 2008
Firstpage
13
Lastpage
18
Abstract
In this paper we propose an on-line self-test architecture for hardware implementations of advanced encryption standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. We show that our solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, it does not weak the device with respect to side-channel attacks based on power analysis.
Keywords
cryptography; fault diagnosis; parallel architectures; advanced encryption standard; on-line fault detection; on-line self-test architecture; parallel architecture; spatial replications; Built-in self-test; Circuit faults; Cryptography; Data security; Decoding; Electrical fault detection; Fault detection; Hardware; Information security; Redundancy; AES cryptochip; On-Line Self-Test; Reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2008 13th European
Conference_Location
Verbania
Print_ISBN
978-0-7695-3150-2
Type
conf
DOI
10.1109/ETS.2008.26
Filename
4556022
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