Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis

Author

Hashimoto, Masanori ; Alnajjar, Dawood ; Konoura, Hiroaki ; Mitsuyama, Yukio ; Shimada, Hajime ; Kobayashi, Kazutoshi ; Kanbara, Hiroyuki ; Ochi, Hiroyuki ; Imagawa, Takashi ; Wakabayashi, Kazutoshi ; Onoye, Takao ; Onodera, Hidetoshi

Author_Institution

Osaka Univ., Suita, Japan

fYear

2015

fDate

19-22 Jan. 2015

Firstpage

14

Lastpage

15

Abstract

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.

Keywords

VLSI; high level synthesis; integrated circuit reliability; reconfigurable architectures; C-to-array application mapping; high-level synthesis; mission-critical applications; mixed-grained reconfigurable VLSI array architecture; proof-of-concept VLSI chip; reliability-configurable mixed-grained reconfigurable array; size 65 nm; Logic gates; Monitoring; Random access memory; Reliability; Tunneling magnetoresistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

978-1-4799-7790-1

Type

conf

DOI

10.1109/ASPDAC.2015.7058923

Filename

7058923