An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main focus of our work is to obtain a modeling of the degradation of selected parameters measurable through at-speed testing. The paper reviews the current approach for reliability characterization and shows the achieved enhancement on efficiency and effectiveness. Results shown are related to experiments run on a vehicle released on a 90 nm technology.