Multiprocessor system verification through behavioral modeling and simulation

The long development times and high costs of multiprocessor (MP) designs arise from their design complexity. To reduce the time and costs, it is critical that design bugs are detected early in the development cycle using design verification tools. The traditional method of hardware design verification is to simulate the actual hardware designs, usually specified in a hardware description language such as VHDL. Two major drawbacks of this methodology when applied to MP systems are the huge size of MP models and the long simulation times. In addition to the difficulty of detecting incorrect behavior in hardware cache coherent systems, MP system verification presents many other challenges as well. In this paper we present a MP verification methodology that lets the actual hardware designs coexist with behavioral models that approximate the functional behavior of the designs they represent. We describe an event-driven behavioral simulation engine that drives the entire simulation, an MP test language, a test executive that injects new transactions into the system, and a coherence monitor that helps detect quickly and efficiently coherency-related bugs in hardware designs