DocumentCode
1998361
Title
Multiprocessor design verification with generated realistic MP programs
Author
Sullivan, Marie ; Wilson, Pete ; Montemayor, Carlos ; Evers, Richard ; Yen, Jen-Tien
Author_Institution
Somerset Design Center, Austin, TX, USA
fYear
1995
fDate
28-31 Mar 1995
Firstpage
389
Lastpage
395
Abstract
High-end microprocessors now tend to be superscalar, to execute operations out of order, and to support shared memory among multiple processors. Verifying the functionality of such a microprocessor using simulation requires many stages, from tests of simple portions of the design, through simple tests of a single processor to complex tests of multiple processors. We followed this strategy using some already existing tools and writing some new tests and tools. We describe in this paper the general strategy and the tool set we created to perform the final simulation stage of design verification: running complex tests on a model of a multiprocessor system. This tool set operates on the principle that tests which mimic real programs are more likely to uncover errors that customers would encounter. Our results show that random realistic tests can get better coverage of common multiprocessor scenarios in fewer cycles than purely random tests
Keywords
digital simulation; formal verification; logic testing; microprocessor chips; multiprocessing systems; design verification; multiple processors; shared memory; simulation stage; superscalar; Automatic programming; Computer bugs; Microprocessors; Monitoring; Out of order; Postal services; Power system modeling; Reduced instruction set computing; System testing; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Communications, 1995., Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix Conference on
Conference_Location
Scottsdale, AZ
Print_ISBN
0-7803-2492-7
Type
conf
DOI
10.1109/PCCC.1995.472463
Filename
472463
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