Evaluation of a crossbar multiplexer in a lithography-based nanowire technology

Silicon Nanowire technology has been demonstrated to be a promising candidate to fabricate nanowire crossbars. The use of such devices in a real architectural as well as in a design environment is an ongoing research topic. In this paper, we investigate the use of a lithography-based industrial process for designing a 4-to-1 multiplexer in a crossbar circuit. We show that by considering the line parasitic, the crossbar demonstrates poor performance in a 65-nm technology, while the area and power savings are about 6x and 1.5x respectively vs. the CMOS implementation. However, extrapolation to the 9-nm node shows a 2x better performance and 67x area saving.